The present invention generally relates to fabrication of semiconductor devices, and more particularly to an improved method for fabricating a semiconductor device having a multi-level interconnection structure.
In modern semiconductor integrated circuits having a high integration density, the multi-level interconnection structure is used commonly for interconnection of various devices within the integrated circuit.
In such semiconductor integrated circuits having the multi-level interconnection structure, it is essential that the device has a planarized top surface so that the conductor pattern provided thereon for forming the interconnection is provided with high precision and with excellent contact to the top surface. When the top surface is not sufficiently planarized, defective interconnection tends to occur and the yield as well as the reliability of the integrated circuit is decreased.
In order to planarize the top surface of semiconductor integrated circuits, a so-called spin-on-glass (SOG) technique is used commonly, wherein the top surface of the integrated circuit on which various interconnections are to be provided, is coated by a solution of organic silicon oxide dissolved into an organic solvent. Such a solution has an extremely low viscosity, and upon evaporation of the solvents, provides an insulating silicon oxide layer called an SOG layer which has a substantially flat top surface suitable for providing the multi-level interconnection structure thereon. However, such a SOG layer has a problem in that, because of the continuous release of organic gases and water even after solidification, defective contacts tend to occur particularly in the contact holes which are provided through the SOG layer in order to achieve an interconnection between metal electrodes such as aluminum deposited thereon and the semiconductor devices buried thereunder.
FIGS. 1A-1G show a conventional process of planarizing the top surface of an integrated circuit by an SOG process. In this example, the integrated circuit includes a MOSFET device as an active device.
Referring to FIG. 1A, a field oxide region 53 for the device isolation is formed on a silicon substrate 51 by the usual selective oxidization of the silicon substrate 51 such that the field oxide region 53 defines a device region 52 in which the MOSFET device is to be formed.
Next, in a step of FIG. 1B, a gate oxide film 54 is provided on the device region 52, and the formation of the polysilicon gate electrode 55 as well as the formation of the source and drain regions 56 and 57, are performed according to the usual MOS process.
In a step of FIG. 1C, the gate oxide film 54 is removed except for the region under the polysilicon gate electrode 55, and the entire structure is covered by a thin oxide film 58 for preventing contamination by impurities. A first insulator layer 59 of phosphosilicate glass (PSG) and the like is provided on the entire top surface, and contact holes 60 are provided through the first insulator layer 59. A first conductor layer (not shown) of aluminum and the like is provided on the first insulator layer 59 so as to make a contact to the underlying semiconductor device through the contact holes 60. The first conductor layer is patterned to form: a source electrode 61 connected to the source region 56; a drain electrode 62 connected to the drain region 57; a first aluminum pattern 63 remaining on the first insulator layer 59 in correspondence to the source region 56; a second aluminum pattern 64 remaining on the first insulator layer 59 in correspondence to the field oxide region 53, and the like.
In a step of FIG. 1D, a thin silicon oxide film 65 is provided so as to cover the aluminum electrodes and patterns 61-64 as well as the first insulator layer 59, by a chemical vapor deposition (CVD) process, and on this silicon oxide film 65, an SOG layer 66 is provided in a form of organic solution. This SOG layer 66 is solidified by curing performed at 400.degree. -450.degree. C.
In a step of FIG. 1E, the SOG layer 66 is subjected to a plasma etching process using a methyl trifluoride (CHF.sub.3) gas, whereby the top surface of the SOG layer 66 is planarized as a result of selective removal of the projections from the layer 66 while leaving the depressions unetched.
Next, in a step of FIG. 1F, a second PSG layer 67 is provided by the CVD process, and a contact hole 68 for inter-layer connection is provided through the PSG layer 67 and the SOG layer 66, and further through the silicon oxide layer 65 so as to expose the aluminum conductor 63 on the first PSG layer 59. Note that, at the side wall of the contact hole 68 thus provided, the SOG layer 66 is exposed.
Finally, in a step of FIG. 1G, an aluminum layer is provided on the second PSG layer 67 including the contact hole 68, and after suitable patterning, an aluminum electrode 69 contacting to the aluminum conductor 63 is obtained. The structure thus obtained may be covered further by an insulator layer not illustrated.
In the foregoing multi-level interconnection structure, it should be noted that the SOG layer 66 is exposed at the side wall of the interlayer contact hole 68. This means that the aluminum electrode 69 makes direct contact to the SOG layer 66 at the side wall of the contact hole 68. The deposition of the aluminum layer forming the electrode 69 is made by sputtering performed under a vacuum environment. A pressure of 10.sup.-3 Torr is used commonly for this purpose. Under such a high vacuum environment, there is a tendency that small amounts of water vapor or gases of organic molecules are continuously released from the SOG layer 66, even after the curing of the SOG layer 66. When water or organic molecules are released, the particle of aluminum deposited in the contact hole 68 becomes excessively coarse as schematically illustrated in FIG. 1G by a numeral 69G, and there is a substantial risk that the contact resistance is increased or the electric contact fails at such a region.
A same problem occurs also when the contact hole 68 is provided at a region of the device where the top surface of the layer underlying the SOG layer 66 is depressed as shown in FIG. 2. In this example, the aluminum conductor 66 is depressed between a pair of gate electrodes 55a and 55b. The existence of such a depressed region on the surface inevitably invites collection of the SOG layer and thus, the SOG layer 66 is exposed at the side wall of the contact hole 68 when the contact hole is provided in correspondence to such a depressed region. As already noted, such an exposure of the SOG layer 66 causes release of gases when the electrode 69 is sputtered, and the problem of unreliable electric contact similarly occurs.